The present invention relates to a counter circuit providing an improved resetting operation.
A conventional counter circuit is shown in FIG. 1. In this circuit, an input reset signal 1 and input clock signal 2 are fed to a counter 3 which produces a counter output 4. Two typical timing charts for the operation of this counter are shown in FIGS. 2 and 3. In either case, when the reset signal 1 changes from "1" to "0", the clock signal 2 rises and thereby causes the counter 3 to advance by one. As will be apparent by comparing FIGS. 2 and 3, the time t for the counter 3 to start counting after reset signal 1 has fallen to the "0" level can vary in the circuit configuration of FIG. 1, and in an extreme case, the time t can be equal to one time period of clock signal 2. Therefore the counter 3 may produce jitter for a duration substantially equal to the period of one clock period if the timing of the release (drop to the "0" level) of the reset signal 1 is poorly adjusted.
An improved counter circuit is shown in FIG. 4. In this circuit, the clock signal 2, before it is fed to the counter 3, is passed through a frequency multiplier 5 which doubles the clock pulse frequency. Two typical timing charts for the operation of this improved counter in response to the reset signal 1 are shown in FIGS. 5 and 6. From these figures, it can be that the maximum value of time t is only about one half that required for the circuit of FIG. 1. This means that the jitter period in the output of the counter 3 is limited to half the period of the clock signal. However, the circuit configuration of FIG. 4 cannot be used if the clock frequency is near the upper limit of the operating frequency of the counter.